SOP Sample for MS in Electrical Engineering in the US

Statement of Purpose

# Introduction

From working on basic logic designs like a D flipflop to working on complex digital designs such as Cortex-A7, I have developed a strong liking for the digital design of any problem. I particularly got interested in the transformation of any mathematical problem into a problem that can be solved using logic gates, and I have decided to work in the VLSI field. All these years I have strived to make this dream a reality. Through my time at [COMPANY_NAME], I have realized that working in transforming mathematical algorithms into a circuit for practical applications inspires me and makes me work harder. I believe that a Master's in Electrical Engineering with an emphasis on VLSI and IC design would help me solve challenges related to the field of electronics and better implement algorithms for emerging technologies.

# Academic Background

Having always been good at math, I took Maths, Physics, and Chemistry in my higher secondary school and secured 99% in maths, which helped me get admission into [UNIVERSITY_NAME], the youngest institute of eminence in India with a 50% waiver of tuition fee. Having always been intrigued by the working of electronic components, I got enrolled in Electronics and Communication Engineering.

During this period I got really interested in courses like Signals and Systems, which introduced me to signal processing as a mathematical tool to solve many real-life problems, and Digital Electronics, which introduced me to digital designs that can represent and manipulate the discrete elements of information, and how boolean algebra is being used to reduce the costs of design and reduce the time of realization of any design. By this interest in digital electronics, I also took a course called "Digital System Design using FPGAs" which really helped me understand all the processes involved in any IC development and manufacturing, and I got fascinated by the use of Verilog as a tool to reduce the design time and get better designs in a short amount of time. This also helped me appreciate the challenges posed while dealing with clocks in designs with respect to static timing analysis. Courses like Creativity, Concept in Design, and Media, Science, and Society helped me in my all-around development.

Since my introduction to signal processing and digital logic, I always wanted to implement Digital Signal Processing algorithms in ICs. It is due to this reason that I did a project "Designing of Sliding DFT Algorithm" on Xilinx FPGA. While working on this project I learned about RTL designing using Verilog. I also learned the importance of synthesizable code for that to be implemented on FPGA. The most important challenge I faced during this time was the conversion of floating-point numbers into fixed-point numbers throughout the flow of the algorithm. I implemented a CORDIC (Coordinate Rotational Digital Computer) algorithm to implement the sine and cosine functions of the DSP algorithm in Verilog and solve the problem efficiently. This also helped me realize the importance of solving the problems in an efficient manner to reduce the time taken for the implementation. This implementation of the Sliding DFT algorithm on FPGA further motivated me to gain an in-depth knowledge of RTL designing and chip designing.

I also completed a minor in Mathematics, and to combine mathematics and signal processing, I completed a project as a part of my final year curriculum, titled "Localization using Graph-based Semi-supervised Learning Methods" for the accurate location of wireless device users in a wireless sensor network (such as wifi network). The two major steps in the project were learning about graph partition by using the Fiedler vector (thresholding the eigenvector with the smallest nonzero eigenvalue) and using graph Slepians to find the optimized embedded distance. This optimization can be done by eigendecomposition of the graph Laplacian to define graph Fourier Transform and to extend conventional signal processing to graphs. This made me appreciate the use of mathematical concepts such as Convex Optimization and Matrix decomposition in signal processing.

# Professional Background

All these performances and the projects helped me secure a job at [COMPANY_NAME]. There, for the first few months as an Engineer Trainee, I studied AMBA and AXI protocols and implemented basic bus transfer logic in Verilog. Later on, I was given the work of RTL integration of technology-specific changes to be made into ARM cores (memory integration and clock gating instances) and the synthesis for these cores (A53, R8, A7, R52).

While working on synthesis (the process of converting RTL into technology mapped gates), I have learned the importance of developing a synthesis flow that will be useful in reducing the time taken for synthesis and which will also help Physical Design engineers post-layout. I also developed and owned SDC constraints for the synthesis and developed SDC to be used during synthesis. I developed different synthesis flows like physical, spatial, and incremental for better timing closure on the Physical Design side and to help meet the frequency, area, and power requirements for the functioning of the chip. Reducing the power numbers of each sequential cell and making the switching activity low for each combinational cell are the major challenges I faced during the synthesis.

Currently, I am working on developing synthesis flow using Design Compiler and also working on enhancing my skills as an STA engineer by working on Cortex-A7 core. I'm also working on enhancing my competency at verification by learning UVM (Universal Verification Methodology) and System Verilog (hardware description language for both design and verification).

# Reasons for Choosing

Understanding the importance of learning advanced chip-design techniques and with the latest technologies emerging each day, I believe that a Master's in Electrical and Computer Engineering with a focus on VLSI design will equip me with a strong technical skillset to solve challenges related to chip design mainly for the fields of signal processing and communications. Ongoing projects and researches in computer engineering at your university, particularly in VLSI design for Low-Density Parity Check (LDPC) codes and researches particularly in optimization for energy-efficient VLSI circuits and on-chip communication fabrics, resonate with my interests and aspirations. Courses like Computational Methods for Integrated System Design and Advances in VLSI Logic Synthesis will help me gain and develop advanced knowledge in the field of chip designing. I am confident that with its high educational standards, this university is an ideal place for my dream of being a prevalent individual in terms of both technology and personality.

I hope the admission committee would give me an opportunity to work with the erudite faculty and realize my dreams.